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quad iec afe quad isdn echocancellation circuit analogue front end peb 24902 version 2.1 quad iec afe quad isdn echocancellation circuit analogue front end pef 24902 version 2.1 data sheet, ds2, jan. 2001 wired communications never stop thinking.
edition 2001-01-23 published by infineon technologies ag, st.-martin-strasse 53, d-81541 mnchen, germany ? infineon technologies ag 2001. all rights reserved. attention please! the information herein is given to describe certain components and shall not be considered as warranted characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. infineon technologies is an approved cecc manufacturer. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office in germany or our infineon technologies representatives worldwide (see address list). warnings due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
wired communications quad iec afe quad isdn echocancellation circuit analogue front end peb 24902 version 2.1 quad iec afe quad isdn echocancellation circuit analogue front end pef 24902 version 2.1 data sheet, ds2, jan. 2001 never stop thinking.
for questions on technology, delivery and prices please contact the infineon technologies offices in germany or the infineon technologies companies and representatives worldwide: see our webpage at http://www.infineon.com peb 24902 revision history: 2001-01-23 ds2 previous version: none page subjects (major changes since last revision) 17, 20, 21 pin addr has to be clamped to v dd rather than to gnd 11 xdnx pins removed from logic symbol
peb 24902 pef 24902 table of contents page data sheet 2001-01-23 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.4 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.5 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 system integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 line card application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 technical description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1 clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1.1 specification of the pll and the 15.36 mhz master clock (pin cl15) . 15 3.1.2 specification of the crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.2 analogue line port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2.1 analogue-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2.2 range function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2.3 digital-to-analogue converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.2.4 external hybrid and transformer parameters . . . . . . . . . . . . . . . . . . . . 27 3.2.5 analogue loop-back function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.2.6 level detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.2.7 power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.2.8 power-on-reset (por) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 3.2.9 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.3 digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.3.1 frame structure on the digital interface in the 2b1q mode . . . . . . . . . 33 3.3.2 frame structure on the digital interface in the 4b3t mode . . . . . . . . . . 34 3.3.3 propagation delay in transmit direction . . . . . . . . . . . . . . . . . . . . . . . . . 36 3.4 boundary scan test controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 4 digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.1 static requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.2 boundary scan timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.1 supply voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.2 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7 environmental requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.1 storage and transportation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.2 operating ambient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.3 thermal contact resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
peb 24902 pef 24902 list of figures page data sheet 2001-01-23 figure 1 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 figure 2 block diagram of the quad iec afe . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 figure 3 pin configuration (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 4 connecting qad iec afe/dfe-t or q . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 5 8 channel lt application (overview) . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 6 8 channel lt application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 7 15.36 mhz clock distribution in multichannel linecards . . . . . . . . . . . 14 figure 8 jitter transfer gain in db . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 9 maximum phase difference due to sinusoidal input jitter . . . . . . . . . 17 figure 10 dac output for a single pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 11 pulse mask for a single +3 pulse (not to scale) . . . . . . . . . . . . . . . . . 24 figure 12 output pulse sample and hold with filter . . . . . . . . . . . . . . . . . . . . . . 25 figure 13 example of external hybrid circuit for 2b1q code . . . . . . . . . . . . . . . 27 figure 14 example of external hybrid circuit for 4b3t code . . . . . . . . . . . . . . . 28 figure 15 block diagram of special functions in the quad iec afe . . . . . . . . . 29 figure 16 power-on-reset behaviour of the afe v1.2 after vdd collapse . . . . . 31 figure 17 frame structure on sdx and sdr in 2b1q mode . . . . . . . . . . . . . . . 34 figure 18 frame structure on sdx/sdr in 4b3t mode . . . . . . . . . . . . . . . . . . . 35 figure 19 definition of transmit pulse start . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 20 boundary scan timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 21 power supply blocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 22 maximum line input current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
peb 24902 pef 24902 list of tables page data sheet 2001-01-23 table 1 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 2 pll characteristcs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 3 pll input requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 4 specification of the crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 5 specified data of the analogue-to-digital converter . . . . . . . . . . . . . . 22 table 6 specified data of the digital-to-analogue-converter . . . . . . . . . . . . . . 26 table 7 transformer parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 8 specified data of the level detection circuit. . . . . . . . . . . . . . . . . . . . 30 table 9 parameters for por activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 10 coding of the 2b1q data (aoutx/boutx) . . . . . . . . . . . . . . . . . . . . . 34 table 11 coding of the 4b3t data pulse (aoutx/boutx) . . . . . . . . . . . . . . . . 35 table 12 pin types and boundary scan cells . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 13 sequence of pins in the boundary scan . . . . . . . . . . . . . . . . . . . . . . . 37 table 14 tap controller instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 15 static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 16 interface signals of afe and dfe-q/dfe-t . . . . . . . . . . . . . . . . . . . . 40 table 17 power consumption (2b1q mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 18 power consumption (4b3t mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 19 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
peb 24902 pef 24902 overview data sheet 1 2001-01-23 1overview the peb 24902 quad iec afe (quadruple isdn echocancellation circuit analogue front end) is part of a 2b1q or 4b3t isdn u-transceiver chip set. up to four lines can be accessed simultaneously by the quad iec afe. the quad iec afe is optimized to work in conjunction with the peb 24901 quad iec dfe-t and the peb 24911 quad iec dfe-q. an integrated pll synchronizes the 15.36 mhz master clock onto the 8 khz or 2048 khz ptt clock. this specification describes the functionality for 2b1q and 4b3t interfaces. all technical descriptions are valid for pef 24902 quad iec afe, too. the only difference between peb 24902 and pef 24902 is the operating ambient temperature, which is extended for pef 24902, see chapter 7.2 .
p-mqfp-64-1,-2 data sheet 2 2001-01-23 quad isdn echocancellation circuit analogue front end quad iec afe peb 24902 version 2.1 cmos type package peb 24902 p-mqfp-64-1 1.1 features ? digital to analogue conversion (transmit pulse) output buffering analogue to digital conversion detection of signal on the line master clock generation by pll p-mqfp-64 package compliant to ansi t1.601 (1992), etsi ts 102080 (1995) jtag boundary scan path compliant to ieee 1149.1
peb 24902 pef 24902 overview data sheet 3 2001-01-23 1.2 logic symbol figure 1 logic symbol aout 0 bout 0 ain 0 bin 0 aout 1 bout 1 ain 1 bin 1 aout 2 bout 2 ain 2 bin 2 aout 3 bout 3 ain 3 bin 3 sdx sdr pdm 0 pdm 1 pdm 2 pdm 3 tdiss tdo tdi tck tms clock cl 15 xin xout v ref3 v ref2 v ref1 v ref0 res pllf addr code gnd d1...2, a0...3 vdd d1...2, a0...3 +5v 0v mode settings boundary scan pins adc outputs serial interface to peb 24901 or peb 24911 analog line ports peb 24902 itl07131.emf
peb 24902 pef 24902 overview data sheet 4 2001-01-23 1.3 functional block diagram figure 2 block diagram of the quad iec afe digital interface buffer level d a a d trafo hybrid analogue in/out dee interface common pll buffer level d a d voltage reference trafo hybrid analogue in/out a ? ? ? ? ? ? ? ? ? ? ? ? itb07132.emf
peb 24902 pef 24902 overview data sheet 5 2001-01-23 1.4 pin configuration figure 3 pin configuration (top view) gnd a2 xdn2 v ref2 ain2 bin2 n.c. tdi tdo tck tms tdiss bin3 v ref3 xdn3 gnd a3 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 ain3 49 48 n.c. 47 aout2 46 vdd a2 45 n.c. 44 bout2 43 gnd d0 sdr n.c. 42 41 pdm2 40 pdm1 39 pdm0 38 vdd d0 37 bout0 36 n.c. 35 vdd a0 34 aout0 33 gnd a0 32 xdn0 31 v ref0 30 ain0 29 bin0 28 addr 27 clock 26 res 25 sdx 24 code 23 pllf 22 bin1 21 ain1 20 v ref1 19 xdn1 18 gnd a1 17 1 n.c. 2 aout3 3 vdd a3 4 n.c. 5 bout3 6 cl15 pdm3 gnd d1 78 xout 9 xin 10 vdd d1 11 n.c. 12 bout1 13 n.c. 14 vdd a1 15 aout1 16 peb 24902 itp07133.emf
peb 24902 pef 24902 overview data sheet 6 2001-01-23 1.5 pin definitions and functions the following tables group the pins according to their functions. they include pin name, pin number, type, a brief description of the function and cross-references referring to the sections in which the pin functions are discussed. table 1 pin definitions and functions pin no. symbol input (i) output (o) description reference section power supply pins 37 vdd d1 5v +/-5% digital supply voltage 5.1 11 vdd d2 34 vdd a0 5v +/-5% analogue supply voltage 5.1 15 vdd a1 46 vdd a2 3vdd a3 42 gnd d1 0v digital 5.1 6gnd d2 32 gnd a0 0v analogue 5.1 17 gnd a1 49 gnd a2 64 gnd a3 30 v ref0 i/o internally generated voltage may be left open or a capacitor, 100 nf, may be connected vs. gnd to maintain compatibility with previous versions 19 v ref1 pd no function, a capacitor, 100 nf, may be connected vs. gnd to maintain compatibility with previous versions 51 v ref2 pd no function, a capacitor, 100 nf, may be connected vs. gnd to maintain compatibility with previous versions
peb 24902 pef 24902 overview data sheet 7 2001-01-23 62 v ref3 pd no function, a capacitor, 100 nf, may be connected vs. gnd to maintain compatibility with previous versions jtag boundary scan 57 tck i test clock. 4.2 58 tms i test mode select, internal pullup. 4.2 55 tdi i test data input, internal pullup. 4.2 56 tdo o test data output. 4.2 59 tdiss i jtag boundary scan disable, active low, internal pullup (i tdiss = -100 a (typ.)). line port pins 29 ain0 i differential u interface input. line port 0 3.2.1 28 bin0 i differential u interface input. line port 0 3.2.1 33 aout0 o differential u interface output. line port 0 3.2.3 36 bout0 o differential u interface output. line port 0 3.2.3 20 ain1 i differential u interface input. line port 1 3.2.1 21 bin1 i differential u interface input. line port 1 3.2.1 16 aout1 o differential u interface output. line port 1 3.2.3 13 bout1 o differential u interface output. line port 1 3.2.3 52 ain2 i differential u interface input. line port 2 3.2.1 table 1 pin definitions and functions (cont ? d) pin no. symbol input (i) output (o) description reference section
peb 24902 pef 24902 overview data sheet 8 2001-01-23 53 bin2 i differential u interface input. line port 2 3.2.1 47 aout2 o differential u interface output. line port 2 3.2.3 44 bout2 o differential u interface output. line port 2 3.2.3 61 ain3 i differential u interface input. line port 3 3.2.1 60 bin3 i differential u interface input. line port 3 3.2.1 2 aout3 o differential u interface output. line port 3 3.2.3 5 bout3 o differential u interface output. line port 3 3.2.3 digital interface 7 cl15 i/o master clock 15.36 mhz. all operations and the data exchange on the digital interface are based on this clock. cl 15 is set to an input at power-on. if a 15.36 mhz clock is generated by the internal pll/ oscillator or if an external clock is provided at xin then cl15 becomes an output and issues this clock. if the pin xin is clamped to low or high then cl15 remains an input and an other device has to provide the 15.36 mhz clock. 3.2.1, 4.2 38 pdm0 o pulse density modulated output of the second-order sigma-delta adc of line port 1 3.2.1, 4.2 39 pdm1 o pulse density modulated output of the second-order sigma-delta adc of line port 2 3.2.1, 4.2 table 1 pin definitions and functions (cont ? d) pin no. symbol input (i) output (o) description reference section
peb 24902 pef 24902 overview data sheet 9 2001-01-23 40 pdm2 o pulse density modulated output of the second-order sigma-delta adc of line port 3 3.2.1, 4.2 8 pdm3 o pulse density modulated output of the second-order sigma-delta adc of line port 4. 3.2.1, 4.2 31 xdn0 i for future use, leave pin open 18 xdn1 i for future use, leave pin open 50 xdn2 i for future use, leave pin open 63 xdn3 i for future use, leave pin open 24 sdx i interface for the transmit and control data. up to eight lines can be multiplexed on sdx. transmission and sampling is based on clock cl15 (15,36 mbit/sec). 3.3, 4.2 41 sdr o level information for the detection of the awake tone. the four lines are multiplexed on sdr. 3.3, 4.2 27 addr i for future use, set to "1". 3.3 23 code i select 2b1q or 4b3t code. code = low sets 2b1q code. 3.3, 3.2.3 25 res i reset and power down of the entire iec quad afe including pll and all four line ports. asynchronous signal, active low. 3.2.9 pll 9 xout o crystal out. 15.36 mhz crystal is connected. leave open if not used. 3.1.2 10 xin i crystal in. a synchronous 15.36 mhz clock signal or 15.36 mhz crystal is connected. clamping xin to either low or high sets cl15 to input. 3.1, 3.1.2 table 1 pin definitions and functions (cont ? d) pin no. symbol input (i) output (o) description reference section
peb 24902 pef 24902 overview data sheet 10 2001-01-23 26 clock i 8 khz or 2048 khz clock as a time base of the 15.36 mhz clock.connect to gnd if not used. 3.1 22 pllf i select corner frequency of pll jitter transfer function. internal pullup resistor (i pllf = -100 a (typ.)). 3.1 table 1 pin definitions and functions (cont ? d) pin no. symbol input (i) output (o) description reference section
peb 24902 pef 24902 system integration data sheet 11 2001-01-23 2 system integration the quad iec afe is optimized for line modules in the central office or access networks (lt function) together with the peb 24901 quad iec dfe-t for 4b3t code or the peb 24911 quad iec dfe-q for 2b1q code. the peb 24911 quad iec dfe-q is footprint compatible to the peb 24901 quad iec dfe-t. this way, one board layout can be used for both line codes simply by putting the appropriate dfe.
peb 24902 pef 24902 system integration data sheet 12 2001-01-23 2.1 line card application the quad iec afe is controlled via the signal at pin sdx. the transmit data is transferred the same way. the quad iec afe can transmit either 2b1q-data or 4b3t-data. setting the pin code to low will result in 2b1q code. for 4b3t code the pin code has to be tied to vdd. the 15.36 mhz master clock is generated with a crystal oscillator and synchronized onto the ptt clock with an integrated pll. fig. 4 shows a 4 channel lt application for 2b1q line code. figure 4 connecting qad iec afe/dfe-t or q figure 5 gives an overview of an 8 channel linecard (2b1q). hybrid hybrid hybrid hybrid sdx sdr 15.36 mhz pdm 0...3 jtag boundary scan iom -2 4 u-interfaces dout din dcl fsc 15.36 mhz peb 24902 quad iec afe peb 24911 quad iec dfe-q tdo tdi tms tck tdo tdi tms tck its06905.vsd addr code peb 24901 quad iec dfe-t vdd or gnd vdd
peb 24902 pef 24902 system integration data sheet 13 2001-01-23 figure 5 8 channel lt application (overview) an 8 channel lt is built with two afe/dfe sets. one quad iec afe generates the master clock for all four devices. the pll in the other quad iec afe is passive. figure 6 8 channel lt application hybrid hybrid hybrid hybrid sdx sdr pdm 0...3 iom -2 8 u-interfaces dout din dcl fsc peb 24902 quad iec afe peb 24911 quad iec dfe-q tdo tdi tms tck tdo tdi tms tck its06906.vsd hybrid hybrid hybrid hybrid sdx sdr pdm 0...3 15.36 mhz clock clock peb 24902 quad iec afe peb 24911 quad iec dfe-q tdo tdi tms tck tdo tdi tms tck 15.36 mhz jtag boundary scan addr code addr code xin peb 24901 quad iec dfe-t peb 24901 quad iec dfe-t vdd or gnd vdd vdd or gnd vdd
peb 24902 pef 24902 system integration data sheet 14 2001-01-23 note: for linecards with 12 or more channels the 15.36 mhz masterclock must not drive more than 3 inputs. the clocking scheme in figure 7 is recommended. figure 7 15.36 mhz clock distribution in multichannel linecards dfe-q/t hybr id hybr id hybr id hybr id 4x u iom ? -2 afe v2.1 pef 24902 15.36mhz cl kchai n2.emf pdm0..3 sdr sdx 15.36mhz dfe-q/t hybr id hybr id hybr id hybr id 4x u afe v2.1 pef 24902 15.36mhz fsc dcl din dout cl15 cl15 cl15 xin xout clock 8/ 2048khz ptt reference cock 1-4mbit/s xin xout clock n.c. gnd cl15 pdm0..3 sdr sdx 15.36mhz hybr id hybr id hybr id hybr id 4x u afe v2.1 pef 24902 15.36mhz xin xout clock n.c. gnd cl15
peb 24902 pef 24902 technical description data sheet 15 2001-01-23 3 technical description 3.1 clock generation all timing signals are derived from a 15.36 mhz system clock. the 15.36 mhz clock can be provided by the quad iec afe by a crystal-based pll, which is synchronized to either an 8 khz or a 2048 khz clock at pin clock. the frequency at pin clock is detected automatically. the pll is set to the nominal frequency either by a por or by a falling edge at the res pin. when the reference clock (clock) is applied, the pll starts to synchronize. the 15.36 mhz clock can also be provided externally at pin cl15 without making use of the internal pll. in this mode the pin xin must be tied to either vdd or gnd. an internal power-on-reset circuitry assures that the pin cl15 is an input until a 15.36 mhz clock is detected at the output of the pll/oscillator. to enable error-free data transport to/from the quad iec dfe-t/q, the clocks dcl and fsc from the iom ? -2-interface must be synchronous to the 15,36 mhz signal. therefore it is recommended to use the same signal for fsc and as input to clock pin at the quad iec afe when the internal pll is used to generate the 15.36 mhz clock. if an other clock source is used for clock, e.g. the 2048 khz dcl, a common time base must be guaranteed. this is usually achieved if fsc is derived from dcl by dividing it directly by 256. any constant phase difference between the time bases of both clocks is possible, but the devices have currently been qualified and released only for using the same fsc signal for the quad iec dfe-t/q and for quad iec afe. 3.1.1 specification of the pll and the 15.36 mhz master clock (pin cl15) the pll is based on a crystal connected to the pins xin and xout. for synchronization of the 15.36 mhz clock up to 16 internal capacitances are connected to xin and xout. the loop filter of the pll is of second order, therefore a sinusoidal input jitter with the angular frequency = 2 f at clock is attenuated by the pll according to the following formula: hj () 2 r ------ j 1 + j r ----- 2 2 r ------ j 1 ++ ------------------------------------------ - =
peb 24902 pef 24902 technical description data sheet 16 2001-01-23 h(j ) is the complex jitter transfer factor r = 2 f r is the angular resonance-frequency of the pll is the damping factor of the pll the maximum phase difference between the external clock and the internal reference, derived from the master clock, due to a sinusoidal input jitter with the angular frequency is given as 1 - h(j ). the magnitude of the jitter transfer function and of the phase difference are illustrated below: figure 8 jitter transfer gain in db 40 30 20 10 0 10 0.01 0.1 1 10 100 1000 10 40 h1 j h1max 1000 0.01 f j fn
peb 24902 pef 24902 technical description data sheet 17 2001-01-23 figure 9 maximum phase difference due to sinusoidal input jitter if the input signal at pin clock disappears being stuck to high or low, the pll continues to generate the cl15 clock. in this case the pll keeps the last setting. the accuracy of the frequency of cl15 degenerates in the long term only due to changes in temperature and ageing. the resonance frequency can be set to two different values using the pin pllf. pllf tied to low sets the pll to a low resonance frequency suited for applications in the access network. pllf tied to high or left open results in a higher resonance frequency for accelerated synchronization. the pllf pin has an internal pull-up resistor. the pll automatically determines whether the frequency at pin clock is 8 khz or 2048 khz . table 2 pll characteristcs parameter limit values unit min. typ. max. f r resonance frequency, pllf = low 1.7 2.0 2.3 hz f r resonance frequency, pllf = high 789hz damping factor 0.7 0.9 1.2 h max maximum jitter amplification 0.9 1.45 2.2 db 80 60 40 20 0 20 0.01 0.1 1 10 100 1000 20 80 h1e j 1000 0.01 f j fn
peb 24902 pef 24902 technical description data sheet 18 2001-01-23 synchronization time of the pll after power on and applying the reference at pin clock, pllf = low 8sec synchronization time of the pll after power on and applying the reference at pin clock, pllf = high 1sec output jitter at cl15 without any jitter in the clock signal (peak-to-peak); jitter frequency > 800 hz 2ns output jitter at cl15 with-out any jitter in the clock signal (peak-to-peak) jitter frequency < 20 hz 80 ns initial accuracy after the loss of the reference clock at clock 0.5 ppm initial accuracy after power on -50 50 ppm start-up time of the oscillator with the crystal suggested below. 0.5 1 ms output current at xout during start-up 0.5 1 ma output current at xout after synchronization 0.5 1 ma table 2 pll characteristcs (cont ? d) parameter limit values unit min. typ. max.
peb 24902 pef 24902 technical description data sheet 19 2001-01-23 table 3 pll input requirements parameter limit values unit min. typ. max. accuracy of the reference at clock to enable synchronization -150 0 +150 ppm peak-to peak jitter of the clock signal during any 125 sec period 70 ns peak-to-peak voltage of a sinusoidal external master clock provided at xin 3.3 v pp low time of the reference at clock 130 ns high time of the reference at clock 130 ns pulse width of the 15mhz clock 26 39 ns
peb 24902 pef 24902 technical description data sheet 20 2001-01-23 3.1.2 specification of the crystal a crystal (serial resonance) has to be connected to xin and xout which shall meet the following specification: note that the load capacitors are integrated in the peb 24902. no additional capacitance has to be connected neither to xin nor to xout. the crystal specifications shall meet the requirements given in table 4 . a suitable type of crystal would be: vibrator: mode of vibration ds fundamental crystal cut ati application hint: parasitic capacitances at xin and xout pin, e.g. due to board capacitances should be below 3 pf. table 4 specification of the crystal parameter min typ max units nominal frequency 15.360000 mhz total frequency range -150 +150 ppm operating frequency c load = 15 pf c load = 7 pf 15.35770 - - 15.36230 mhz mhz current 1 2 ma load capacitance 9.8 10.2 pf overall tolerance ? f/f 60 ppm resonance resistance r r 30 ohm shunt capacitance c 0 7pf motional capacitance c 1 25 ff overall pullability +- 210 ppm
peb 24902 pef 24902 technical description data sheet 21 2001-01-23 3.2 analogue line port the quad iec afe chip gives access to four line ports. the signal to be transmitted is issued differentially at pins aout0..3 and bout0..3. the input is differentially sampled at ain0..3 and bin0..3. each line port consists of three main function blocks: ? the analogue-to-digital converter in the receive path ? the digital-to-analogue converter in the transmit path ? the output buffer in the transmit path furthermore a line port contains some special functions. these are: ? analogue test loop-back ? level detect function 3.2.1 analogue-to-digital converter a first order low pass anti alias filter is provided at the input of the adc. the adc is a sigma-delta modulator of second order using a clock rate of 15.36 mhz. during normal operation the adc evaluates the signal at ainx and binx. the adc evaluates the signal at aoutx and boutx while the analogue loop-back is activated. the maximum peak input voltage between ainx and binx is defined as the minimum input voltage that results in a continuous series of high or low at the pdmx pin. a larger input signal will be clipped. an increasing positive voltage at ainx - binx will result in an increasing number of high states at the pdmx pin. hence, the maximum positive voltage at ainx - binx results in a series of high whereas the maximum negative voltage results in a series of low. the average percentage of high states obtained with a given input voltage is referred to as gain of the adc. it is expressed in %/volt. the adc offset is the difference in % from the ideal 50 % high states with no input signal, transferred back to the input voltage using the adc gain. the maximum signal to noise ratio is achieved by signals of approximately 65% of the maximum peak input signal voltage. the signal to noise ratio is evaluated with a digital third order low pass filter applied to the digital data stream. the filter transfer function zeroes are at 80 khz, 80 khz and 160 khz. 3.2.2 range function in case the signal input is too high (low attenuation on short loops), the range function can be activated. the range function attenuates the received signal internally by 6 db. the range function is activated by setting the range bit on sdx to one.
peb 24902 pef 24902 technical description data sheet 22 2001-01-23 table 5 specified data of the analogue-to-digital converter parameter limit values unit test condition min. typ. max. signal/noise (sine wave 1.5 vpp between ainx/binx) 70 72 db range function deacti- vated, all line ports sending random 2b1q pattern into 98 ? load signal/(noise+ distortion) (sine wave 0.4 vpp between ainx/binx) 59.5 61.5 db range function deacti- vated, all line ports sending random 2b1q pattern into 98 ? load signal/(noise+distortion) (sine wave 1.5 vpp between ainx/binx) 65 68 db range function deactivated signal/(noise+distortion) (sine wave 2.0 vpp between ainx/binx) 60 db range function deactivated signal/(noise + distortion) (sine wave 3 vpp between ainx/ binx) 60 db range function activated signal/noise (sine wave 3 vpp between ainx/ binx) 65 68 db range function activated, all line ports sending random 2b1q pattern into 98 ? load signal/(noise + distortion) (sine wave 4 vpp between ainx/ binx) 50 db range function activated signal/(noise+distortion) (sine wave 4.6 vpp between ainx/binx) 35 db range function activated dc offset voltage 35 mv range function deactivated dc offset voltage 70 mv range function activated adc gain 28 33 38 %/v range function deactivated adc gain 14 16.5 19 %/v range function activated
peb 24902 pef 24902 technical description data sheet 23 2001-01-23 3.2.3 digital-to-analogue converter the output pulse is shaped by a special dac. the dac is optimized for excellent matching between positive and negative pulses and high linearity. it uses a fully differential switched capacitor approach. the staircase-like output signal of the dac drives the output buffers. the shape of a dac output signal is shown below, the peak amplitude is normalized to one. this signal is fed to an rc low pass of first order. figure 10 dac output for a single pulse attenuation of the range function 5.45 6 6.25 db impedance between ainx and binx 100 k ? input capacitance at ainx and binx 3pf input voltage range at ainx and binx gnd vdd common mode rejection ratio 40 db f < 80 khz power supply rejection ratio 40 db f < 80 khz power supply rejection ratio 55 db 80 khz < f < 20 mhz anti alias filter corner frequency 1.1 1.6 2.3 mhz table 5 specified data of the analogue-to-digital converter (cont ? d) parameter limit values unit test condition min. typ. max. 1.0 0.75 0.5 123456789 1718 25 x t0 t0 = 0.78 s (2b1q code) resp. 0.52 s (4b3t code) itd07135.vsd 0.25
peb 24902 pef 24902 technical description data sheet 24 2001-01-23 the duration of each pulse is 24 steps, with t = 0.78 sec per step for 2b1q code and 0.52 sec per step for 4b3t code. the pulse rate is one pulse per 16 steps, e.g. 80 khz for 2b1q code and 120 khz for 4b3t code. thus, the subsequent pulses are overlapping for a duration of 8 steps. the output stage consists of two identical buffers, operated in a differential mode. the buffers are optimized for: ? high output swing ? high linearity ? low quiescent current to minimize power consumption the pulse mask for a single +3 2b1q-pulse (+1 4b3t pulse) measured between aoutx and boutx at a load of 98 ? = is given in figure 11 . 98 ? represents the nominal load in a 2b1q system when the line is substituted by a 135 ? register. figure 11 pulse mask for a single +3 pulse (not to scale) the pulse mask for a +1 pulse is obtained by dividing all voltages in figure 11 by 3. negative pulses are described by the corresponding negative voltages. the pulse as given in figure 11 is passing a sample and hold circuit and a first order rc low pass filter. the sample period is 0.78 s (2b1q code) or 0.52 s (4b3t code). -0.4 t 0.4 t 3.3 v 3.1 v 0.5 t -0.5 t t -0.75 t 0 16 mv -16 mv 16 mv 100 mv -16 mv 50t t = 12.5 s (2b1q) or 8.333 s (4b3t) itd07138.vsd
peb 24902 pef 24902 technical description data sheet 25 2001-01-23 the switch is closed during 1/3 of the sample period. hence, during 2 / 3 of the time, the output signal does not change. this way, a settling behavior is achieved which is slowed down by a factor of three compared to the cut-off frequency of the rc low pass filter. figure 12 output pulse sample and hold with filter the relative amplitudes of the single steps of the pulse are given below. step numbers are as referred to in figure 10 . steps 9 to 16 have a level of 1.0. the descending steps are defined as follows: static tolerances of the step sizes are such that the pulse mask as given in figure 11 is provided. dynamic tolerances are such that the nonlinearity values as given in table 6 are reached. the signal to noise plus distortion ratio is measured using an evenly distributed but otherwise random sequence of +3, +1, -1, -3 (2b1q code) or +1, 0, -1 (4b3t code) driving 98 ? in series with a dc voltage. the output signal at aoutx and boutx has to be weighted with a low pass filter from 0 to 80 khz (2b1q code) or 120 khz (4b3t code), respectively, to get the specified sum of noise and total harmonic distortion as given in period after step no. 0 1 2 3 4 5 6 7 8 relative level 0 0.0625 0.1875 0.3125 0.4375 0.5625 0.6875 0.8125 0.9375 period after step no. 17 18 19 20 21 22 23 24 25 relative level 0.9375 0.8125 0.6875 0.5625 0.4375 0.3125 0.1875 0.0625 0 s/h d a buffer aoutx / boutx its07139.emf
peb 24902 pef 24902 technical description data sheet 26 2001-01-23 table 6 . any linear mismatch between 3 and 1 symbols is cancelled for the s/n measurements. table 6 specified data of the digital-to-analogue-converter parameter limit values unit test condition min. typ. max. absolute peak voltage measured for a single +3 or -3 pulse between aoutx and boutx 3.1 3.2 3.3 v 98 ? load between aoutx and boutx absolute peak voltage measured for a single +1 or -1 pulse between aoutx and boutx 1.033 1.067 1.1 v 98 ? load between aoutx and boutx common mode dc level 2.05 2.375 2.6 v offset between aoutx and boutx - 35.5 35.5 mv ratio between 1 and 3 symbols 0.3283 0.3333 0.3383 variation of the signal amplitude measured over a period of 1 min. 1% peak-to-peak output jitter measured with a high-pass filter of 30 hz cut-off frequency 1.3 nsec jitter free 15.36 mhz clock peak-to-peak output jitter measured without the high-pass filter 6.5 nsec signal / (noise + distortion) driving 98 ? in series with 6.8 v dc 26 db signal / (noise + distortion) driving 98 ? in series with 3.2 v dc 53 db signal / (noise + distortion) driving 98 ? in series with 0.5 v dc 63 68 db corner frequency of the dac rc low pass filter 420 620 900 khz output impedance aoutx/ boutx 1 2 6 4 12 ? ? power-up power-down
peb 24902 pef 24902 technical description data sheet 27 2001-01-23 3.2.4 external hybrid and transformer parameters for the 2b1q-code and the 4b3t-code different external hybrids are suggested in figures 13 and 14 . these hybrids will work correctly with an according transformer as described in table 7 . please note that table 7 gives typical transformer parameters and is not intended to be a complete transformer description. transformer linearity must be such that no significant destortion is added to the signal passing the echo path from aoutx/boutx to ainx/binx. figure 13 example of external hybrid circuit for 2b1q code
peb 24902 pef 24902 technical description data sheet 28 2001-01-23 figure 14 example of external hybrid circuit for 4b3t code table 7 transformer parameters parameter symbol 2b1q 4b3t unit transformation ratio; device side : line side n 1:1.6 1:1.32 main inductance of windings on the line side l h 14.5 7.9 mh leakage inductance of windings on the line side l s = 90 50 h coupling capacitance between the windings on the device side and the windings on the line side c k = 100 = 75 pf dc resistance of the windings on device side r cu, b 2.8 1.9 ? dc resistance of the windings on line side r cu, l 2.7 1.3 ?
peb 24902 pef 24902 technical description data sheet 29 2001-01-23 3.2.5 analogue loop-back function the loop-back bit (loop) set to one on sdx activates an internal analogue loop-back. this loop-back is closed near the u interface. signals received on ainx / binx will neither be evaluated nor recognized by the adc. the output signal is attenuated by 17 db and fed to the inputs of the adc and level detect circuit instead. it is still available at aoutx / boutx. figure 15 shows a schematic of the loop-back function. figure 15 block diagram of special functions in the quad iec afe 3.2.6 level detect the level detect circuit evaluates the differential signal between ainx and binx. level detect is not affected by the range setting nor by the analog loop-back. it is also active during power down. the level detection is preceded by a first order low pass filter. the detected level is communicated to the quad iec dfe on sdr. the detected level is updated every 12.5 sec (2b1q) or every 8.33 sec (4b3t). if the input signal exceeds the threshold once during this time, the level bit is set to one, otherwise it is set to zero. the level bit is repeated on sdr during the whole time slot associated with the corresponding line port. buffer - 17 db - 6db loop d d a a aoutx/boutx loop range range ainx/binx lowpass level detection itb07141.vsd
peb 24902 pef 24902 technical description data sheet 30 2001-01-23 3.2.7 power down transmit path, receive path and auxiliary functions of the analog line port are switched to a low power consuming mode when the power down function is activated. this implies the following: ? the adc: the relevant pin pdmx is tied to gnd. ? the dac and the output buffer:the pins aoutx boutx are tied to gnd. ? the internal dc voltage reference is switched off. ? the range and the loop functions are deactivated. the digital interface, the pll, and the level detection are not affected by the powerdown. 3.2.8 power-on-reset (por) when applying power to the quad iec afe an internal power-on-reset is generated to reset the pll/oscillator* and to set cl15 to an input. if a 15.36 mhz clock is generated by the internal pll/oscillator or if an external clock is provided at xin then cl15 becomes an output and issues this clock. if the supply voltage starts from a vdd voltage below 1.0v the afe guarantees proper por function with the restriction that the rising v dd slope has to be minor 5v/4s. the por function is enabled again if the supply voltage v dd drops below 1.0v for a minimum period of 80ns (see figure 16 and table 9). * note: the res pin must be at "1" level during por to enable the reset of the pll/oscillator. table 8 specified data of the level detection circuit parameter limit values unit min. typ. max. cut-off frequency of the input filter 90 160 230 khz threshold of level detect (2b1q) 4 20 mv threshold of level detect (4b3t) 10 30 mv dc level of level detect (common mode level) 0 3 v
peb 24902 pef 24902 technical description data sheet 31 2001-01-23 figure 16 power-on-reset behaviour of the afe v1.2 after v dd collapse table 9 parameters for por activation parameter limit values unit min. typ. max. maximum v dd slope (rising or falling) 5v/ 4s por enable threshold 1.0 4.5 v v dd -below-1v-time 80 ns v dd time 5v 1v 0v min 80ns por_behavi our .vsd
peb 24902 pef 24902 technical description data sheet 32 2001-01-23 3.2.9 reset the reset is activated by setting pin res to low. the following functions are reset: ? the reset activates the powerdown of all line ports. ? the data on sdx is ignored during reset. ? sdr is set to low ? the range and the loop functions of all line ports are deactivated ? on a falling edge at the res pin, the pll is reset to it ? s nominal frequency and starts to resynchronize after 130 ns. note: a running 15.36 mhz cl15 clock is required for this function. all settings are maintained until res is high and the digital interface is synchronized.
peb 24902 pef 24902 technical description data sheet 33 2001-01-23 3.3 digital interface on the digital interface transmit and receive data is exchanged as well as control information for the start-up procedure. the adc output is transferred to the quad iec dfe t or quad iec dfe q on the signals pdm0..pdm3. the timing of all signals in 2b1q mode as well as 4b3t mode is based on the 15.36 mhz clock which is provided by the quad iec afe. the transmit data, powerup/down, range function and loopback are transferred on sdx, and the level status on sdr for all line ports. eight time slots contain the data for up to eight line ports. the quad iec afe operates in slots 0,2,4,6. the remaining slots are reserved for future use. the allocation of these time slots is done by the ninth time slot, a 24 bit synch. word on sdx, that consists of all zeros. the other time slots with transmission data start with a one. therefore the first one after at least 24 subsequent zeros must be the first bit of time slot no. 0. this information is also used to determine the status of synchronization of the digital interface after reset. the line code independent data on sdx: nop : the no-operation-bit is set to zero if none of the control bits (pdow, range and loop) shall be changed. the values of the control bits of the assigned line port is latched. the states of the control bits on sdx are ignored, they should be set to zero to reduce any digital cross-talk to the analog signals. the nopq bit is set to one if at least one of the control bits shall be changed. in this case all control bits are transmitted with their current values. pdow: if the pdow bit is set to one, the assigned line port is switched to powerdown. otherwise it is switched to powerup. range: range = one activates the range function, otherwise the range function is deactivated. "range function activated" refers to high input levels. loop: loop = one activates the loop function, i.e. the loop is closed. otherwise the line port is in normal operation. sy: first bit of the time slots with transmission data. for synchronization and bit allocation on sdx and sdr, sy is set to one. nt: this bit is for future use. it is set to"0" by the existing dfes. "0": reserved bit. reserved bits are currently not defined and shall be set to zero. some of these bits may be used for test purposes or can be assigned a function in later versions. 3.3.1 frame structure on the digital interface in the 2b1q mode the 192 available bits during a 80 khz period (related to the 15.36 mhz clock) are divided into the 9 slots of which 8 slots are 21 bits long used for data transmission.
peb 24902 pef 24902 technical description data sheet 34 2001-01-23 the status on sdr is synchronized to sdx. each time slot on sdr carries the corresponding ld bit during the last 20 bits of the slot. figure 17 frame structure on sdx and sdr in 2b1q mode the 2b1q data is coded with the bits td2, td1, td0: 3.3.2 frame structure on the digital interface in the 4b3t mode the 128 available bits during a 120 khz period (related to the 15.36 mhz clock) are divided into 9 slots of which 8 slots are 13 bits long used for data transmission. the status on sdr is synchronized to sdx. each time slot on sdr carries the corresponding ld bit during the last 12 bits of the slot. table 10 coding of the 2b1q data (aoutx/boutx) 2b1q data td2 td1 td0 0 ? 1 ?? don t care ?? don t care ? ? 30 0 0 ? 10 0 1 + 3 0 1 0 + 1 0 1 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 sdx sdr sy=1td 2td 1td 0 pdowlooprangent"0""0" "0""0" "0""0" "0""0" "0" "0" "0""0" 0ld nopq 0 21 42 63 84 105 126 147 168 191 slot 0 slot 1 slot 2 slot 3 slot 4 slot 5 slot 6 slot 7 synch. word 21 bit 21 bit 21 bit 21 bit 21 bit 21 bit 21 bit 21 bit 24 bit itd07142.vsd
peb 24902 pef 24902 technical description data sheet 35 2001-01-23 figure 18 frame structure on sdx/sdr in 4b3t mode the 4b3t data is coded with the bits td1, td0: table 11 coding of the 4b3t data pulse (aoutx/boutx) 4b3t data pulse td1 td0 000 + 1 1 0 ? 111
peb 24902 pef 24902 technical description data sheet 36 2001-01-23 3.3.3 propagation delay in transmit direction the start of the transmit pulse is defined as given in figure 19 : figure 19 definition of transmit pulse start the delay in transmit direction depends on the slot x on sdx. the pulses on the four lines are equally spaced in time while the transmit bits on sdx are not. the delay is defined as the time from the end of last bit of the slot x on sdx until the start of the pulse at aoutx/boutx as given in figure 19. the delay is (3x + 27) * 65 ns.
peb 24902 pef 24902 technical description data sheet 37 2001-01-23 3.4 boundary scan test controller the quad iec afe provides a boundary scan support for a cost effective board testing. it consists of: ? complete boundary scan for 11 signals (pins) according to ieee std. 1149.1 specification. ? test access port controller (tap) ? four dedicated pins (tck, tms, tdi, tdo) ? one 32-bit idcode register ? pin t dis s tied to low disables the complete boundary scan test controller boundary scan the following pins are included in the boundary scan: addr, cl15, clock, code, pdm0, pdm1, pdm2, pdm3, res , sdr, sdx depending on the pin functionality one, two or three boundary scan cells are provided. table 12 pin types and boundary scan cells when the tap controller is in the appropriate mode data is shifted into or out of the boundary scan via the pins tdi/tdo using the 6.25 mhz clock on pin tck. pin type number of boundary scan cells usage input 1 input output 2 output, enable i/o 3 input, output, enable table 13 sequence of pins in the boundary scan boundary scan number tdi ?? > pin number pin name type number of scan cells default value tdi ?? > 1 7 cl15 i/o 3 0 0 0 28pdm3o21 0 323codei10 424sdxi10 525res i1 0 626clocki10 727addri10
peb 24902 pef 24902 technical description data sheet 38 2001-01-23 tap controller the test access port (tap) controller implements the state machine defined in the jtag standard ieee std. 1149.1. transitions on the pin tms cause the tap controller to perform a state change. the following instructions are executable. extest is used to examine the board interconnections. when the tap controller is in the state "update dr", all output pins are updated with the falling edge of tck. when it has entered state "capture dr" the levels of all input pins are latched with the rising edge of tck. the in/out shifting of the scan vectors is typically done using the instruction sample/preload. intest supports internal chip testing. when the tap controller is in the state "update dr", all inputs are updated internally with the falling edge of tck. when it has entered state "capture dr" the levels of all outputs are latched with the rising edge of tck. the in/out shifting of the scan vectors is typically done using the instruction sample/preload. note: 001 (intest) is the default value of the instruction register. 838pdm0o20 0 939pdm1o20 0 10 40 pdm2 o 2 1 0 11 41 sdr o 2 0 1 table 14 tap controller instructions code instruction function 000 extest external testing 001 intest internal testing 010 sample/preload snap-shot testing 011 idcode reading id code 11x bypass bypass operation table 13 sequence of pins in the boundary scan (cont ? d) boundary scan number tdi ?? > pin number pin name type number of scan cells default value tdi ?? >
peb 24902 pef 24902 technical description data sheet 39 2001-01-23 sample/preload provides a snap-shot of the pin level during normal operation or is used to preload (tdi) / shift out (tdo) the boundary scan with a test vector. both activities are transparent to the system functionality. idcode register the 32-bit identification register is serially read out via tdo. it contains the version number (4 bits), the device code (16 bits) and the manufacturer code (11 bits). the lsb is fixed to "1". note: note:in the state "test logic reset" the code "0011" is loaded into the instruction code register. bypass , a bit entering tdi is shifted to tdo after one tck clock cycle, e.g. to skip testing of selected ics on a printed circuit board. version device code manufacturer code output 0011 0000 0000 0010 0110 0000 1000 001 1 --> tdo
peb 24902 pef 24902 digital interface data sheet 40 2001-01-23 4 digital interface unless otherwise specified, the static and dynamic limits apply over a supply voltage range from 4.75 to 5.25 v and over the temperature range as specified in section 7.2 . 4.1 static requirements the ac characteristics of the afe-interface pins are optimized to fit to dfe-q/t versions 1.1/1.2/1.3/2.1 if the following loads are no exceeded. if dfe-q/t of versions 1.x are used, it is required, that both devices are supplied by the same 5 volt source (vdd/ gnd). no intermediating circuitry shall be inserted when connecting the afe to dfe-q/t. table 15 static characteristics parameter symbol limit values unit test condition min. typ. max. high level input voltage v ih 2.4 v dd + 0.3 v low level input voltage v il ? 0.3 0.8 v low level input leakage current v il ? 10 av in = gnd high level input leakage current i ih 10 av in = vdd high level output voltage (pin cl15) v oh 4.4 v i oh = 5 ma high level output voltage (all other outputs) v oh 4.0 v i oh = 1 ma low level output voltage v ol 0.33 v i ol = 1 ma input capacitance c in 10 pf table 16 interface signals of afe and dfe-q/dfe-t pin signal driving device max. capacitve load cl15 afe 50 pf sdr afe 20 pf pdm0..3 afe 20 pf sdx dfe-t/dfe-q 20 pf
peb 24902 pef 24902 digital interface data sheet 41 2001-01-23 4.2 boundary scan timing figure 20 boundary scan timing parameter symbol limit values unit min. max. test clock period t tcp 160 - ns test clock period low t tcpl 70 - ns test clock period high t tcph 70 - ns tms set-up time to tck t mss 30 - ns tms hold time from tck t msh 30 - ns tdi set-up time to tck t dis 30 - ns tdi hold time from tck t dih 30 - ns tdo valid delay from tck t dod -60ns tdo tdi tms tck t tcp t tcph t tcpl t mss t msh t dod t dih itt07144.vsd t dis
peb 24902 pef 24902 power supply data sheet 42 2001-01-23 5 power supply 5.1 supply voltages vdd d1 to gnd d1 = +5v 0,25v vdd d2 to gnd d2 = +5v 0,25v vdd a1 to gnd a1 = +5v 0,25v vdd a2 to gnd a2 = +5v 0,25v vdd a3 to gnd a3 = +5v 0,25v vdd a4 to gnd a4 = +5v 0,25v the following blocking circuitry is suggested. figure 21 power supply blocking vdd d2 100nf 100nf 100nf 100nf 100nf 100nf gnd 5 v 1f these capacitors should be located as near to the pins as possible 1) 1) 1) 1) 1) 1) 1) bl ocki ng_caps_afe.vsd vdd d1 vdd a4 vdd a3 vdd a2 vdd a1 gnd d2 gnd d1 gnd a4 gnd a3 gnd a2 gnd a1
peb 24902 pef 24902 power supply data sheet 43 2001-01-23 5.2 power consumption all measurements with random 2b+d data in active states, 5v (0 c - 70 c). table 17 power consumption (2b1q mode) table 18 power consumption (4b3t mode) parameter symbol limit values unit comment min. typ. max. 98 ? load at aoutx/boutx 725 840 mw all line ports are in power up 98 ? load at aoutx/boutx 200 250 mw one line port is in power up all inputs are tied to v dd or gnd 25 50 mw all line ports are in power-down parameter symbol limit values unit comment min. typ. max. 172 ? load at aoutx/boutx 665 775 mw all line ports are in power up 172 ? load at aoutx/boutx 185 235 mw one line port is in power up all inputs are tied to v dd or gnd 25 50 mw all line ports are in power-down
peb 24902 pef 24902 maximum ratings data sheet 44 2001-01-23 6 maximum ratings stresses above those listed in table 19 may cause permanent damage to the device. exposure to conditions beyond those indicated in section 5.1 of this specification may affect device reliability. this is a stress rating only and functional operation of the device under these conditions or at any other condition beyond those indicated in the operational conditions of this specification is not implied. it is not implied, that more than one of these conditions can be applied simultaneously. line overload protection the maximum input current (under over-voltage conditions) is given as a function of the width of a rectangular input current pulse. for the destruction current limits refer to figure 22 : table 19 maximum ratings parameter limit values unit min. max. positive supply voltage 7.0 v voltage applied at any input -0.3 vdd + 0.3 max. 7.0 v voltage applied at at the line port outputs -0.3 vdd + 0.3 max. 7.0 v voltage between gndx to any other gndx 0.3 v voltage between vddx to any other vddx 0.3 v maximum surge voltage applied at the line port inputs esd hardness according to mil-standard 883d method 3015.7
peb 24902 pef 24902 maximum ratings data sheet 45 2001-01-23 figure 22 maximum line input current
peb 24902 pef 24902 environmental requirements data sheet 46 2001-01-23 7 environmental requirements 7.1 storage and transportation the rated (limited capability) storage and transportation temperature range prior to printed board assembly shall be as follows: - 65 to +150 c (without supply voltage) 7.2 operating ambient the operating ambient temperature for standard and extended temperature versions shall be within the limits as follows: peb 24902 0 c to +70 c (standard version) pef 24902 ? 40 c to +85 c (extended temperature range version) 7.3 thermal contact resistance the thermal contact resistance is: r thu (silicon -environment): 55 kelvin/watt
peb 24902 pef 24902 package outlines data sheet 47 2001-01-23 8 package outlines plastic package, p-mqfp-64-1 (plastic metric quad flat package) sorts of packing package outlines for tubes, trays etc. are contained in our data book ? package information ? . dimensions in mm smd = surface mounted device
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